Founded in 2016
CPU design, debugging and design optimization (timing, area, power and latency) including architecture and micro-architecture of various parts of CPU using 5nm ASIC technologyRTL coding in Verilog and SystemVerilogResponsible for Memory Controller (DDR4/5), Mesh IO Ring, EXE unit (integer instructio...
Jakub Chovanec
Hardware Design Engineer
Pini Herman
Senior Director Solution Engineering
Robert Cisar
Business Development Manager
Matej Demes
Marketing Specialist
Bill Radke
Architecture Manager
Marwan Ajam Oghli
Business Development Specialist
Adrian Vycital
Board Member
Vladimir Sedlak
Hardware Design Engineer
Michal Chovanec
Artificial Intelligence Researcher